This invention relates to a synchronized clock generating apparatus which can provide a high frequency clock signal which is synchronized with an externally applied asynchronous trigger input signal.
The only conventional method for improving the synchronization precision of an output clock which is synchronized with an asynchronous trigger input has been to increase the frequency of an input clock signal.
For instance, for a high synchronization precision of 1 ns, an input clock signal at a high frequency of 1 GHz is required. However, increasing the frequency of the input clock signal to 1 GHz will cause problems, such as the generation of internal noise and generation of undesirable radiations, and accordingly, such a method is not feasible.
Furthermore, to form a 1 GHz clock signal generating circuit and its associated frequency-divider by ordinary CMOS circuit techniques is not easy, and therefore, it requires a special technique, such as the very high speed bipolar technique, which considerably increases the manufacturing costs of the apparatus.
FIG. 1 is a block diagram of a conventional synchronized clock generating apparatus, and FIG. 2 shows various waveforms that represent the operation of the apparatus of FIG. 1. A high frequency clock signal CK generated by a high frequency clock signal generating circuit 102 is applied to a clock input terminal A of a counter 103 and also to a clock input terminal A of a frequency-divider 104. A trigger input terminal B of counter 103 receives, as a count enable signal, a trigger signal TR via a trigger input terminal 100 from a trigger signal source 105. The trigger signal TR is asynchronous with the clock signal CK.
The counter 103 starts counting the number of clock pulses of the high frequency clock signal CK from high frequency clock generating circuit 102, immediately after a transition t.sub.1 (FIG. 2) in the trigger signal TR from a high logic level H to a low logic level L. When the count reaches a prescribed value, for example, 3, counter 103 generates a frequency-division enable signal DE for application to an enable signal input terminal B of frequency-divider 104. In response to the frequency-division enable signal DE applied to the enable signal input terminal B, frequency-divider 104 starts frequency-division of the high frequency clock signal CK and produces an output clock signal CK.sub.out having a transition occurring every four cycles, for example, of the high frequency clock signal CK.
With the above-described conventional clock signal generating apparatus, the output clock signal CK.sub.out will be produced with the same timing even if the H-to-L transition t.sub.1 in the trigger signal TR varies within a range T defined by broken lines. Accordingly, in order to increase the precision of synchronization of the output clock signal CK.sub.out, the frequency of the high frequency clock signal CK must be increased. The synchronization precision becomes higher as the frequency of the high frequency clock signal CK becomes higher. Thus, the relationship between them can be expressed as Synchronization Precision.apprxeq.Period of High Frequency Clock Signal.